How AI Is Pushing the Semiconductor Supply Chain to the Limit

ELI5 / TLDR

The world makes about a trillion chips a year, and a single dust mote can kill one. The fanciest ones — the GPUs powering the AI boom — depend on a supply chain so concentrated it’s almost embarrassing: one Dutch company (ASML) makes the lithography machines, one Taiwanese company (TSMC) prints over 90% of the leading-edge chips, and almost everyone else in the industry is downstream of those two. AI demand has stretched this fragile pipeline thin, governments are throwing tens of billions at reshoring, and a Taiwan conflict could erase $10 trillion of global GDP. Meanwhile a quieter buildout — analog chips, TI in Sherman, Texas — is happening because even an AI server needs the boring chips that move power around.

The Full Story

A trillion-dollar industry priced like jewelry

Bloomberg opens with the staging — clean rooms cleaner than operating theatres, single skin cells killing chips, $30,000 dies moved in armored vehicles. The figures justify the theater: a trillion semiconductors ship every year (about 100 per person on Earth), and the industry is on track for $1 trillion in revenue in 2026. AI is the reason it suddenly feels glamorous instead of cyclical:

My beat went from obscure backwater that people had sort of heard of to being the center of technology.

What used to be a boom-bust commodity business — ride the PC refresh, slump, ride the smartphone refresh, slump — has turned into something that looks more like a sustained capex supercycle, because data center buildouts don’t stop the way iPhone upgrades did.

ASML, or: how to print something smaller than a virus

Lithography is the load-bearing trick. You shine light through a mask onto a silicon wafer and burn the chip’s circuits into it. The catch: features on a leading-edge chip are now ~50,000 times thinner than a human hair, smaller than a virus. Visible light is too coarse. ASML had to invent its way to extreme ultraviolet (EUV), a wavelength that doesn’t naturally exist at Earth’s surface — they generate it by zapping tin droplets with a laser.

The machine itself is the size of a double-decker bus, weighs as much as a blue whale, and costs about $400 million. Inside, the reticle stage accelerates at 20G — four times the peak G-load of a fighter jet — copying a pattern onto a wafer hundreds of thousands of times in roughly twelve seconds. Every leading-edge fab on Earth either uses ASML’s machines or is queuing up to.

All of the manufacturers of the most advanced chip in the world, whether they say it publicly or not, use ASML’s machines or are about to use ASML’s machines.

There is no plan B. This is one company, in one country, with a multi-decade lead.

AMD and the shape of an AI chip

AMD is the customer side of the leading-edge story. The video walks through the physical contrast: a CPU is one piece of silicon, a server chip is bigger, an AI chip is something else entirely — a central compute die surrounded by eight HBM (high-bandwidth memory) chiplets, each stacked twelve layers high. The interesting word is “stacked.” The frontier of advanced chips is no longer just about shrinking transistors flat on a wafer; it’s about gluing many specialized dies together vertically, with memory packed against logic so the GPU doesn’t starve.

AI chips were already a quarter of all chip sales in 2025. By 2029, more than half. AI infrastructure spending is approaching $1 trillion. The reason this matters: chip demand used to be paced by consumer refresh cycles. Now it’s paced by hyperscaler capex, which has a different temperament — fewer cycles, deeper pockets.

TSMC: the bottleneck of bottlenecks

Then we land in Taiwan. TSMC manufactures over 90% of the world’s most advanced chips, almost entirely from gigafabs on a single island. Bloomberg’s framing is precise:

It’s basically the bottleneck of all bottlenecks. Smack dab in the middle of a very complex supply chain with no simple alternative.

Why is everything clustered in Taiwan? Because “bringing up a fab” — getting a new line operational — is brutally hard. If a working fab is next door, you copy it. The logistics, the suppliers, the talent, the muscle memory all argue for proximity. Clusters are efficient. Clusters are also fragile: an earthquake, a typhoon, a pandemic, or a geopolitical shock cascades immediately. Taiwan had its strongest earthquake in 25 years recently. COVID jammed the auto industry for two years.

And then there’s the China question. A February 2026 Bloomberg economics estimate puts the global GDP hit from a Taiwan conflict at $10 trillion. The whole modern economy is, as one analyst flatly puts it, likely to collapse if something happens to the Taiwanese chip ecosystem.

China’s parallel build, and the sanctions wall

China is the world’s largest chip market and was, until recently, a chip-manufacturing also-ran — under 10% domestic supply, mostly trailing-edge. Then in 2023 Huawei shipped an advanced China-made chip that nobody outside expected so soon, and Bloomberg reporters found three secret fabs in Guangdong. Building a leading-edge plant costs at least $30 billion in capital, which is why everyone assumed it couldn’t be done quietly.

The state response has been straightforward: a $50 billion national chip fund, an additional $70 billion under consideration, plus Alibaba and Tencent funding domestic startups. The wall is ASML — EUV machines are export-controlled, China can’t buy them, and you can’t really do leading-edge logic without them. So China is the world’s biggest analog chip producer (the boring stuff), advancing on advanced nodes through workarounds and brute capital, and stuck behind a moving US sanctions regime on the frontier.

Reshoring: Arizona, Sherman, and the cost of doing it at home

In 1990, the US made nearly 40% of the world’s chips. By 2024, ~10%. The 2022 CHIPS Act put $52 billion on the table to reverse that. TSMC has committed $165 billion to its Arizona fabs and is scheduled for $6.6 billion in direct CHIPS funding. Texas Instruments is sinking $60 billion into 300mm analog manufacturing, including a four-fab Sherman, Texas mega-site that will eventually cover 5.5 million square feet — the footprint of two Empire State Buildings — fully automated, with 15 miles of overhead track moving wafers around.

The economics don’t really work without subsidy. As one analyst dryly notes, the US has never been the cheapest place to make chips — labor is expensive, regulation is heavy. The pitch isn’t cost; it’s resilience and defense. Satellites need chips that survive space radiation. The Pentagon doesn’t want that supply chain ending in Hsinchu.

The TI angle is also interesting: they’re not chasing AI chips, they’re betting that an AI buildout floods the world with demand for the cheap, high-volume analog chips that nobody talks about. You cannot build a data center without thousands of power-management and sensor chips. The chip company that makes the boring ones, at scale, on bigger wafers (300mm gives 2.3x the chips per wafer vs. 200mm), wins on margin even if the spotlight is elsewhere.

Key Takeaways

~1 trillion semiconductors shipped per year; industry revenue projected at $1 trillion in 2026
AI chips: >25% of all chips sold in 2025 → projected >50% by 2029; AI infrastructure spend approaching $1 trillion
ASML EUV machines: ~$400M each, double-decker-bus sized, blue-whale weight; reticle stage accelerates at 20G; the only path to leading-edge chips
TSMC: >90% of the world’s most advanced chips, almost all from Taiwan gigafabs
Taiwan conflict downside: ~$10 trillion in lost global GDP (Bloomberg Economics, Feb 2026)
Leading-edge fab cost: >$30 billion to build
CHIPS Act: $52B (2022); TSMC Arizona commitment $165B, with $6.6B direct CHIPS funding
TI Sherman, Texas: $60B advanced-manufacturing bet; 5.5M sq ft mega-site (~2 Empire State Buildings); 15 miles of automated overhead track
Wafer math: 300mm wafer gives 2.3x the surface area of 200mm
US chip share: ~40% in 1990 → ~10% in 2024
China: $50B national chip fund + ~$70B more under consideration; <10% domestic supply historically; Huawei advanced-chip surprise in 2023
AI chip architecture: central logic die + 8 HBM chiplets stacked 12 layers high — packaging now matters as much as transistor shrink

Claude’s Take

Bloomberg Primers are usually solid for what they are: the explainer-with-aerial-shots format, accurate, well-sourced, intentionally non-threatening. This one delivers the standard set of facts — ASML, TSMC, Taiwan, CHIPS Act — competently, and the field visits to AMD, TI Sherman, and an Arizona fab give it a tactile edge most explainers miss. The HBM-stacking demo at AMD and the wafer-size comparison at TI are the kind of details you only get on camera.

What it doesn’t do, and never really tries to do, is the harder layer underneath. The CoWoS packaging chokepoint — the actual binding constraint on Nvidia/AMD AI chip output for the past two years — gets a single visual nod (“stacked twelve layers high”) with no explanation. HBM supply (SK Hynix, Samsung, Micron) is invisible. The interplay between EUV machine throughput, TSMC node ramps, and packaging capacity — which is where the real bottleneck story lives — is replaced with the more telegenic TSMC-is-90% framing. If you’ve read Chip War or follow Dylan Patel, this is mostly familiar ground.

That said: as a 24-minute orientation, it’s well-paced, the experts are real, and the geopolitics is presented soberly without fearmongering. Solid 7. Good for someone getting their bearings, slightly thin if you’re already tracking the space.

How AI Is Pushing the Semiconductor Supply Chain to the Limit | Bloomberg Primer