Embedded Memories: The Next Generation

ELI5/TLDR

A computer chip is fast, but the memory that feeds it data usually sits in a separate chip nearby. Reaching over to it wastes time and power. So engineers started building little patches of memory right onto the chip itself, next to the part that does the thinking. For decades two flavors of this on-chip memory ruled. Both are now hitting walls they can’t shrink past, and a small zoo of weird new memories, ones that store data by flipping tiny magnets or growing microscopic wires, is lining up to replace them.

The Full Story

Why memory wants to move onto the chip

A chip’s logic, the part that actually computes, runs hot and fast. The data it needs lives in memory. If that memory sits in a separate module across the circuit board, every fetch is a little road trip: slower, and it burns energy. The fix is to put some memory directly onto the same piece of silicon, sitting right beside the logic. That is “embedded memory.” Closer means faster and cheaper to reach.

The catch is that memory and logic like to be manufactured in different ways. Forcing them onto one chip means adding extra steps, and every extra step costs money and risks ruining the chip. Hold that thought, because it’s the tension running through the entire video.

The three friends, and where they went

Think of a “process node” as the size of the smallest features a factory can carve, measured in nanometers. Smaller usually means denser and better. Forty years ago, three kinds of standalone memory chips existed:

SRAM — static RAM. Fast, made entirely out of transistors (the tiny on/off switches that all chips are built from).
DRAM — dynamic RAM. Dense, made from one transistor plus one capacitor (a capacitor is a tiny bucket that holds electric charge).
Flash — the kind in USB sticks and SSDs. Keeps its data even with the power off.

Over the decades these drifted apart, “like high school friends after graduation.” DRAM grew tall skinny capacitors stacked vertically. Flash split into two styles, NOR and NAND, and NAND eventually became 3D NAND, layers stacked like lasagna, one of the densest things in all of chipmaking.

SRAM: the gold standard that got fat

SRAM never won as a standalone product, but it found its calling embedded on chips. Because it’s built purely from transistors, the same kind logic uses, you can make it alongside the logic without any extra manufacturing masks (a mask is a stencil used to pattern each layer; more masks, more cost). In the late 1980s CPU makers started embedding SRAM as “cache,” a small fast scratchpad for hot data. It’s still the single largest embedded memory market.

But SRAM is, in the video’s words, “a thicc boy.” The standard cell uses six transistors to store one bit, versus DRAM’s one-transistor-one-capacitor. That was fine while transistors kept shrinking. They’ve mostly stopped. SRAM density is now so stuck that fabs use it as a bragging metric:

One of the few hard numbers that TSMC has publicly announced about their N2 process node is how it can stuff more SRAM onto the die.

It got extreme. In the mid-2000s, some high-end CPUs were up to 70% SRAM by area. A computing chip that’s mostly memory.

eDRAM: denser, but a pain to make

If SRAM is bloated, why not embed DRAM instead? Same one-transistor-one-capacitor trick, now on-die: five to six times denser than SRAM, and about a third of the power. The Xbox 360 used it. The problem is that DRAM’s manufacturing recipe differs from logic’s, so embedding it adds four to six extra masks. More cost, more chips ruined. eDRAM’s momentum has faded, though academics still love it for research.

eFlash: the one that remembers

SRAM and eDRAM are both “volatile,” meaning power off, data gone. Often you want memory that holds its data without power. Enter embedded flash, or eFlash.

Flash stores a bit by trapping electrons in a “floating gate,” an isolated pocket inside the transistor. Trapped electrons change how much voltage the transistor needs to switch, and you read that difference as a 1 or 0. eFlash uses the NOR style, which lets you read any single cell directly. (NAND, the denser cousin, chains cells together so you can only read in big blocks, no good for embedded use.)

eFlash has real downsides. Writing it needs high voltages, 9 to 18 volts, to shove electrons through the insulator, while logic transistors run on about 1 volt. You have to wall the flash off so it doesn’t fry its neighbors. It writes slowly, wears out after enough write cycles, and adds six to eight extra masks, even more than eDRAM. Still, it boots fast, sips power, and survives the heat and vibration of a car engine bay. That’s why it dominates microcontrollers (MCUs), the small simple “whole computer on one chip” brains running in cars and appliances. eFlash in automotive MCUs is usually the second-largest embedded memory market after SRAM.

The wall eFlash can’t climb

eFlash stops scaling at around 28 nanometers, the last generation before chips went 3D. Below that, the floating gate holds only a hundred-odd electrons. Lose a few and the bit degrades, and with insulating layers now atomically thin, leakage is far more likely.

NAND solved this by going vertical, the 3D NAND lasagna. But that trick doesn’t transfer to eFlash, and stacking a whole different transistor type on a logic chip could mean up to ten extra masks. Economically hopeless. So eFlash has no clear successor, which is exactly the gap the next-generation memories are racing to fill.

MRAM: storing bits in magnets

Here’s the conceptual leap. Old memories store a bit as charge. The new ones store it as resistance, how hard it is to push current through.

MRAM uses a tiny sandwich called a Magnetic Tunnel Junction: two magnetic layers with a sliver of insulator (about 1-2 nanometers of magnesium oxide) between them. The bottom magnet is fixed. The top one can be flipped. When both point the same way, current flows easily, low resistance. When they point opposite ways, resistance jumps. “It is like twisting a faucet open or closed.” Low and high map to 0 and 1.

The early version flipped the magnet with a magnetic field, which got unreliable as cells shrank, thermal jitter could flip a bit by accident. The modern version, STT-MRAM (spin-transfer torque), shoots a special current straight through the junction to flip the top magnet directly. It’s non-volatile, needs no refreshing, takes ~43% less area than SRAM at the 5nm node, writes in under 10 nanoseconds (DRAM-fast, and far quicker than flash), and endures heavy use. The hard part is making it: that 1-2nm oxide barrier is fussy, prone to defects like oxygen creeping in during etching (“bird’s beaking”). And at the smallest nodes, the write current it needs is more than the delicate tiny transistors can comfortably deliver.

ReRAM: growing and erasing a tiny wire

The other contender, ReRAM, also stores bits as resistance but does it differently, and “kind of fun.” Picture a metal-oxide layer between two electrodes. Apply a voltage and a microscopic conductive filament, possibly as small as 10 by 10 nanometers, grows across the gap, a wire punched through an insulator. That’s the low-resistance state. Reverse the voltage and the filament dissolves. “Very elegant, very simple concept.”

ReRAM needs fewer extra masks than the other non-volatile options, scales down well, and is fast and low-power. The weakness is consistency: forming and breaking the filament is “inherently random,” so behavior varies cell to cell, and nobody’s quite sure how many cycles it survives before getting flaky. Israel’s Weebit Nano licenses the IP; TSMC offers it as an option.

Why eFlash refuses to die

Despite TSMC and Samsung pushing MRAM and ReRAM, eFlash hangs on. In the world of car-grade microcontrollers, reliability beats raw speed, and eFlash is proven on cheap trailing-edge nodes like 65nm. The industry is conservative and won’t switch “until they have to.” The newcomers’ main hope is AI: because embedded memory sits right next to the logic, it could shortcut the bottleneck where the processor sits idle waiting for data to arrive (the “Von Neumann bottleneck”), or run low-power on-device AI. As the video puts it, the technologies “seem to have gotten ahead of the use case.”

Key Takeaways

Embedded memory exists to dodge the off-chip trip. Going to a separate memory module costs time and energy; putting memory beside the logic is faster and cheaper to access.
The fundamental tension is manufacturing masks. Memory and logic use different recipes. Each memory type added to a logic chip adds extra masks (eDRAM: 4-6, eFlash: 6-8, 3D-stacked: up to 10), and each mask adds cost and the chance of ruining the chip.
SRAM is fast and mask-free but bloated. Six transistors per bit, and since transistors barely shrink anymore, its density is stuck, so much so that fabs quote SRAM density to advertise new nodes.
DRAM density comes from 1 transistor + 1 capacitor; SRAM uses 6 transistors and no capacitor. That structural difference is why eDRAM is 5-6x denser than SRAM.
Volatile vs non-volatile is the dividing line. SRAM and DRAM forget when power is cut; flash, MRAM, and ReRAM remember. Non-volatile is what microcontrollers need.
NOR allows random single-cell access; NAND chains cells for density but only allows block access. eFlash is NOR; that’s why embedded NAND isn’t a thing.
Flash stores a bit as trapped electrons in a floating gate, and writing it needs 9-18V versus logic’s ~1V, forcing isolation so it doesn’t fry neighbors.
eFlash hits a hard scaling wall at ~28nm (the last flat/planar node) because the floating gate holds only ~100 electrons and thin oxides leak.
The next-gen memories store bits as electrical resistance, not charge. This is the key conceptual shift away from the old paradigm.
STT-MRAM flips a tiny magnet using current through a magnetic tunnel junction: non-volatile, ~43% smaller than SRAM at 5nm, sub-10ns writes, durable. Bottleneck is fabricating the fussy 1-2nm oxide barrier and delivering enough write current at tiny nodes.
ReRAM grows/dissolves a microscopic conductive filament through an insulator to switch states. Simple and scalable, but the process is inherently random, hurting consistency and endurance certainty.
The semiconductor industry is conservative by design. eFlash survives because car-grade MCUs value reliability on cheap mature nodes over the unproven speed of newcomers.

Claude’s Take

Asianometry is reliably good at this exact thing: taking a corner of the chip world that sounds impenetrable and laying it out without dumbing it down. The framing here is clean, the three friends growing apart, then each hitting its personal wall, then the contenders to replace the one that’s most stuck. You come away actually understanding why SRAM is fat, why eFlash can’t go below 28nm, and what’s genuinely novel about storing a bit as resistance instead of charge.

The honest part is the ending, which doesn’t oversell. MRAM and ReRAM have been “the next big thing” for years, and the video says plainly that they’ve “gotten ahead of the use case.” That’s the correct read. Both have real flaws, MRAM’s finicky oxide barrier and write-current problem, ReRAM’s randomness, and the incumbent it’s meant to kill keeps shrugging it off because reliability on a cheap old node beats speed nobody’s asking for yet. The AI angle is presented as a hope, not a done deal, which is the right level of skepticism.

Docking a couple points only because it’s necessarily a survey, broad rather than deep, and a few mechanisms (spin-transfer torque, how a read distinguishes resistance states) get the gloss rather than the full treatment. But for what it is, an orientation map of embedded memory and where it’s headed, it’s excellent. 8/10.